Y.I LEE 工程师
2021-01-06 11:50:05
-现任玖芯半导体有限公司工程师
-ITM 半导体: Assembly process& quality eng’r
-Physical Stack up Analysis: Die Stacking, Thin Wafer
-Material Analysis: For back grinding, Die attach material, Wafer sawing(mechanical & laser)&EMC etc.
-New technology and equipment buy off Slurry study for wafer backgrinding on Cu trace in Nand Flash tech.
-Die attach material study for thin wafer process.